Fast transmission gate switch

ABSTRACT

A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

BACKGROUND OF THE INVENTION

[0001] This invention relates in general to signal switches and inparticular, to a fast transmission gate switch, particularly useful forswitching digital logic signals.

[0002] With the advent of very large-scale integrated circuits, the sizeof devices manufactured has been shrinking and the speed of the deviceshas continually increased. Most of the efforts, however, have beendirected to designs where many circuits and the connections between themare made in the same medium such as a silicon chip. Since all thecircuit components being fabricated are done in the same medium, devicesmay be made smaller by improved techniques such as improved lithography.By reducing the sizes of the devices and the lengths of the connectionsbetween them, the speed of the device is increased due to a decrease inthe inductances, resistances and capacitances of individual devices andof the connections between them.

[0003] Board level designs have not kept pace with the above-describeddevelopment in very large-scale integrated circuits. Printed circuitboard designs frequently have large capacitances which slow down signalpropagation. Thus if two high speed logic chips are connected through aslower device, the overall speed of the system is determined by theslowest component, namely, the slow connecting device. Passive switchingdevices such as transmission gates have been used in printed circuitboard level designs for switching signals between digital logic devices.The slow speed of this type of switches determines the speed of signaltransmission even though the two logic devices may operate at muchhigher speeds. It is therefore desirable to provide a stand-aloneswitching device which is much faster than the conventional passivetransmission gate.

[0004] In one type of improved switching circuits that is frequentlyused, instead of a passive switch, an active device such as a logicbuffer is used. While a buffer used as a switch causes a delay that isless than that caused by the conventional passive transmission gateswitch, the delay caused by such buffers may nevertheless be excessiveand undesirable for some high speed applications. It is thus desirableto provide a high speed switch that causes less delay than the abovedescribed switches.

SUMMARY OF THE INVENTION

[0005] The switching device of this invention has two input/output portsfor passing or blocking signals between the two ports of the device. Thedevice comprises a transistor having a first and a second terminal and acontrol terminal. The first and second terminals are connected betweenthe two ports. The transistor thereby passes signals between the twoports when the transistor is turned on and blocks the passage of signalsbetween the two ports when the transistor is turned off. The resistancebetween the first and second terminals is less than about 10 ohms whenthe transistor is turned on. The device further comprises means forapplying a switching signal to the control terminal of the transistorfor turning it on or off. In the preferred embodiment, the capacitancebetween the first or second terminal and a reference potential is lessthan about 50 pF when the transistor is turned on.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a schematic circuit diagram of a passive transmissiongate switch illustrating a conventional design.

[0007]FIG. 2 is a schematic view of an active switch device using anenabled buffer to illustrate another conventional design.

[0008]FIG. 3 is a perspective view of a MOS transistor useful forillustrating the invention.

[0009]FIG. 4 is a cross-sectional view of the transistor of FIG. 3.

[0010]FIG. 5 is a schematic circuit diagram of a transmission gateswitch and of a driver and receiver to illustrate the Preferredembodiment of the invention.

[0011]FIG. 6 is a schematic circuit diagram of a transmission gateswitch and of a driver and receiver to illustrate an alternativeembodiment of the invention.

[0012]FIGS. 7 and 8 are schematic circuit diagrams of two differenttransmission gate switches to illustrate additional alternativeembodiments of the invention.

[0013]FIG. 9 is a schematic view of a bus switch for switching signalsbetween two sets of bus lines to illustrate applications of theinvention.

[0014]FIG. 10 is a schematic circuit diagram of a bus exchange switch toillustrate applications of the invention.

[0015]FIGS. 11A, 11B are schematic circuit diagrams illustrating theoperation of the circuit in FIG. 5.

[0016]FIG. 12A is a block diagram of a computer system illustrating theapplications of the invention.

[0017]FIG. 12B is a timing diagram illustrating the operation of thesystem in FIG. 12A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018]FIG. 1 is a schematic circuit diagram of a conventionaltransmission gate switch 20 connected to the output of a driver 22 andthe input of a receiver 24 at nodes A, B respectively. The signal to beswitched appears at the output of driver 22. When switch 20 connectsnodes A and B, such signal is transmitted to node B and appears at theinput of receiver 24. Driver 22 and receiver 24 may each be part ofanother circuit chip package mounted on a printed circuit board whereswitch 20 is connected by conductive traces through nodes A, B to thesechip packages.

[0019] Switch 20 has resistance R so that the switch may be representedconceptually as a resistor 26 in series with a pure switch 28 as shownin FIG. 1. The conductive traces 32 connecting switch 20 to driver 22and receiver 24 have inherent capacitances and so does receiver 24 asseen by a signal propagating between nodes A and B. The transmissiongate switch 20 itself also has capacitance. The total capacitance of theconductive traces, receiver 24 and switch 20 as seen by a signalpropagating from A to B is commonly known as the stray capacitance andis represented conceptually as capacitor 30 in FIG. 1. Thus a measure ofthe delay of the signal propagating from node A to node B is given bythe RC time constant, or the product of the resistance of resistor 26and the capacitance of capacitor 30.

[0020] For typical printed circuit board designs, a typical straycapacitance value exclusive of the effect of the switch itself is about50 pF. Therefore, if switch 20 has a large resistance value, the RC timeconstant will be large, resulting in a significant signal delay when thesignal propagates from A to B. A standard transmission gate switch isCMOS 4016 integrated circuit. The typical resistance values of existingtransmission gate switches such as the 4016 are in the range of100-1,000 ohms. This type of switches would therefore introduce a delayof the order of 50-500 nanoseconds, assuming a 50 pF stray capacitance.Such delay is unacceptable for switching high speed signals required inmany computer and logic applications. For this reason, the 4016 typeswitch is more commonly used in analog circuits and seldom in boardlevel computer or digital logic designs. For the latter applications,active logic devices such as industry standard 74F244 buffers have beenused such as shown in FIG. 2. To simplify the discussion, identicalcomponents and the figures of this application are identified by thesame numerals.

[0021] As shown in FIGS. 1 and 2, transmission gate switch 20 has beenreplaced by a logic buffer 40 in FIG. 2. Driver 22 and receiver 24 maybe part of computer or logic chip packages mounted on a printed circuitboard and connected to buffer 40 by conductive traces 32 on the board.Buffer 40, however, introduces a delay of its own because of theinherent speed limitations of active logic. The 74F244 buffer introducesa delay of about 6.5 nanoseconds. Thus while using a logic buffer 40 toreplace switch 20 does reduce the delay in signal transmission, it isdifficult to further reduce the delay introduced by the buffer itself.It is therefore desirable to provide an improved switching device wherethe above-described difficulties are alleviated.

[0022] This invention is based on the observation that, by employing atransistor having low inherent resistance, the signal delay of theswitch can be further reduced to a value much below that of the activebuffers in FIG. 2.

[0023]FIG. 3 is a perspective view of a MOS transistor useful forillustrating the invention. FIG. 4 is a cross-sectional view of thetransistor of FIG. 3. As shown in FIGS. 3 and 4, the channel length of aMOS type transistor is the distance L between the source and drainregions of the transistor while the channel width is the dimension W ofthe transistor in the direction where the cross-sectional configurationof the transistor does not change. Another common definition of thechannel length is the width of the gate that overlaps the active regionof the transistor between the source and drain. Another commondefinition of the channel width is the length of the gate overlappingthe active region of the transistor between the source and drain.

[0024]FIG. 5 is a schematic circuit diagram of a transmission gateswitch and of a driver and receiver to illustrate the preferredembodiment of the invention. As shown in FIG. 5, the transmission gate100 includes a N-channel MOS transistor 102 and a driver 104 forcontrolling the gate of transistor 102 in response to an external signalfrom node C. The channel length of transistor 102 is not more than 1.5microns, preferably not more than 1 micron. The channel width oftransistor 102 is more than about 1,000 microns and preferably 1,200microns or more. In reference to FIGS. 3 and 4, by reducing the channellength, the resistance of the resistor is reduced since current carriershave a shorter distance to travel in order to conduct current betweennodes A, B. By using a transistor with large channel width compared tothe transistors in the 4016 type gate, the resistance of transistor 102is further reduced in comparison. With the above-described design fortransistor 102, it is found that the inherent resistance of transmissiongate switch 100 between nodes A, B when the transistor 102 is turned on(on-resistance) can be reduced to a value of no more than 10 ohms.Applicant has discovered that in some designs, the resistance of switch100 when transistor 102 is turned on may be reduced to a value in therange of 2-3 ohms. Shorter channel lengths also results in reducedcapacitance of transistor 102. A typical capacitance value of switch 100is in the range of a few pF and is not significant compared to thetypical stray capacitance of 50 pF. Thus, it is preferable for thecapacitance of the transistor as seen at terminals A or B to be 50 pF orless, so that the switch itself does not introduce too much of a signaldelay. Such capacitance is, of course, measured at terminals A or B inreference to ground or another reference potential.

[0025] The above-described transmission gate switch 100 may be used toadvantageously replace active logic devices such as 74F244, 74F245 forswitching high speed digital logic signals in a board level design. Thereplacement of the active device with device 100 will greatly reduce thepropagation delay, logic noise (e.g., “ground bounce” noise) and powerdissipation associated with the active device replaced. Switch 100 isalso inherently bi-directional. Other embodiments of the switchdescribed below in reference to FIGS. 5-8 also have similar advantages.

[0026] Switch 100 may be modified by replacing transistor 102 by aP-channel transistor where the polarity of the signal for controllingthe gate of the transistor has been adjusted if necessary to accommodatea P-channel device. Where the P-channel device also has theabove-described channel lengths and widths, switch 100 may beconstructed to have a on-resistance of not more than 10 ohms.

[0027] The gate of transistor 102 is controlled by the output of adriver 104 which may include a pair of P-channel and N-channel resistorsconnected in parallel between node C and the gate of transistor 102. Inorder to increase the speed of switching, the pair of transistors indriver 104 would preferably each have a channel length of 1.5 microns orless. Where a driver 104 and transistor 102 are fabricated as astand-alone integrated circuit device 100 using the same fabricationtechnology, the transistors in device 100 may be grown so that all thetransistors in the device have short channel lengths. Where device 100is fabricated as an integrated circuit, it can be made in the form of apackage having three pins for connection to nodes A, B and C.

[0028]FIG. 6 is a schematic circuit diagram of a transmission gateswitch and of a driver and receiver to illustrate an alternativeembodiment of the invention. As shown in FIG. 6, switch 150 includes apair of N-channel transistor 102 and a P-channel transistor 152connected in parallel between nodes A, B. The gate of transistor 102 iscontrolled by a driver 104 as in FIG. 5 and the gate of transistor 152is controlled by the output of driver 154 whose input is connected tothe output of driver 104. Where both transistors 102, 152 have thechannel lengths and widths as those described above for transistor 102,the on-resistance of switch 150 would be 10 ohms or less.

[0029]FIGS. 7 and 8 are schematic circuit diagrams of two differenttransmission gate switches to illustrate additional alternativeembodiments of the invention. Bipolar transistors typically haveon-resistances of less than 10 ohms so that they may be used instead ofMOS transistor 102. Such configuration is illustrated in switch 200 ofFIG. 7. While a npn transistor 202 is employed in switch 200, it will beunderstood that a pnp type transistor may be used instead and is withinthe scope of the invention. As shown in FIG. 7, the base of transistor202 is controlled by the output of a driver 204 through resistor 206.Driver 204 may be one of the 7400 TTL series of logic gates, such as the74F04 gate.

[0030] In FIG. 8, a back to back connection of two npn transistors 202and 252 are shown for switch 250, although 2 pnp transistors may be usedinstead. It is known that for a bipolar transistor, unlike a MOStransistor, the current flowing between the collector and emitter isgreater in one direction than the other. By placing two transistors 202,252 in two parallel paths and connected to nodes A, B so that each nodeis connected to a collector of one transistor and the emitter of theother transistor, currents will flow through the path of lesserresistance in each direction so that the amount of current that needs tobe pumped through the switch is reduced.

[0031]FIG. 9 is a schematic circuit diagram of a CMOS bus switch deviceemploying the invention for switching the signals between two sets ofbus lines. Quality Semiconductor, Inc. of Santa Clara, Calif., assigneeof the present application, has employed the present invention for busswitches such as one shown in FIG. 9 in product 74FCT3384. As shown inFIG. 9, switch device 500 is a high speed TTL bus connect device. Whenenabled, the bus switch device directly connects two buses with theconnection resistance of less than 5 ohms. The five lines A0, A1, A2,A3, A4 in bus A are each connected through a transistor 102 to the buslines B0, B1, B2, B3, B4 respectively. The five transistors 102connecting A0-A4 to B0-B4 have their gates controlled by the output ofdriver 104′. Similarly, the five lines A5-A9 in bus A are connected tothe respective one of the five bus lines B5-B9 in bus B throughtransistors 102 whose gates are controlled by the outputs of a driver104″. Thus switch device 500 includes ten switches 102 arranged as twobanks of five and controlled by two different drivers. This allowsswitch device 500 to be used as a 10-bit switch or as a 5-bit, 2-to-1multiplexer. This is accomplished by electrically connecting the pairsof lines B0-B5, B1-B6, B2-B7, B3-B8 and B4-B9. In such event, when theoutput of driver 104′ is high, the signals present on lines A0-A4 willbe transmitted to the B bus whereas if the output of driver 104″ ishigh, the signals present on lines A5-A9 will be transmitted to the Bbus instead to accomplish the 2-to-1 multiplexer function. When theoutput of one of the two drivers is low, the transistors driven by thedriver will be turned off and the respective bus lines connected by suchtransistors are disconnected from one another. The above-describedfunction is summarized in the Function Table below. Function Table: BEABEB B0-4 B5-9 Function H H Hi-Z Hi-Z Disconnect L H A0-4 Hi-Z Connect HL Hi-Z A5-9 Connect L L A0-4 A5-9 Connect

[0032] Device 500 includes in essence ten switches, where each switchincludes an N-channel MOS transistor driven by a CMOS gate. When theswitch is enabled, the gate of the N-channel transistor is at Vcc (+5volts) and the device is on. These devices have an on resistance of lessthan 5 ohms for voltages near ground and will drive in excess of 64 mAeach. The resistance rises somewhat as the I/O voltage rises from a TTLlow of 0.0 volts to a TTL high of 2.4 volts. In this region the A and Bpins are solidly connected, and the bus switch is specified in the samemanner as a TTL device over this range. As the I/O voltage rises toapproximately 4.0 volts, the transistor turns off. This corresponds to atypical TTL high of 3.5 to 4.0 volts.

[0033]FIG. 10 is a schematic circuit diagram of a CMOS bus exchangeswitch 600 in another product 74FCT3383. Switch 600 comprises two banksof ten switches arranged to gate through or exchange two banks of fivesignals. This allows switch 600 to be used as a 10-bit switch or as a5-bit, two-way bus exchange device. Switch 600 is particularly usefulfor exchange and routing operations such as byte swap, crossbarmatrices, and RAM sharing. The functions of switch 600 are summarized inthe Table below. Function Table: BE BX B0-8 B1-9 Function H X Hi-Z Hi-ZDisconnect L L A0-8 A1-9 Connect L H A1-9 A0-8 Exchange

[0034] The bus switch provides a path for a driving device to drivecapacitance to ground and to drive capacitance up from ground. This isshown in FIGS. 11A, 11B. When the A (or B) input is driven to a TTL lowof 0.0 volts, the N-channel transistor is fully on and the B (or A)output will follow it. Likewise, when the A (or B) input is driven froma TTL low of 0.0 volts to a TTL high, the capacitor side of theN-channel switch is at 0.0 volts, the switch is fully on and the B (orA) output will follow it through threshold and beyond. This means thatthe rise and fall time characteristics and waveforms of the B (or A)output will be determined by the TTL driver, not the bus switch. Theswitch introduces insignificant propagation delay.

[0035] When the bus switch is disabled, the N-channel transistor gate isat 0.0 volts, and the transistor is off. By the nature of the N-channeltransistor design, the A and B pins are fully isolated when thetransistor is off. Leakage and capacitance is to the chip substrate(i.e., ground) rather than between input and output. This minimizesfeedthrough in the off state. Because only an N-channel transistor isused, either A or B pin(s) can be taken to Vcc and above, and the devicecan be powered down without loading either bus.

[0036] The bus switch can replace drivers and transceivers in systems ifbus repowering is not required. Since the bus switch directly connectstwo buses, it provides no drive of its own but relies on the device thatis driving data onto the connected buses. If the additional loading ofthe connected bus is small enough, there is a net gain in speed. Forexample, the sensitivity to loading of a driver such as the 74FCT244 istypically 2 ns/100 pF. If the connected bus adds 50 pF of loading theadded delay will be 1 ns. This is much less than the 4-10 ns delay ofthe buffer or transceiver the bus switch replaces.

[0037]FIG. 12A shows bus switches (labeled 3384) of the type in FIG. 9used to allow the memory for a DSP slave processor to be accessed by thehost processor. A 33 mHz TMS320C30 system is shown with a 16Kx32 SRAM asits program and data storage memory. The SRAM is connected to the DSPCPU by a 3384 device, allowing full speed operation while the CPU isrunning. This saves 10 ns over using conventional fast buffers andtransceivers, i.e., 5 ns for a 244 address buffer to the SRAM and 5 nsfor a 245 address transceiver from the SRAM, as shown in the timingdiagrams in FIG. 12B. This allows using SRAMs with 35 ns Taa (accesstime) instead of 25 ns. Between calculations, the 3384 devicesdisconnect the SRAM from the DSP CPU and connect it to the host CPU,allowing the host to write data in before the DSP calculation and readdata out after.

I claim:
 1. An integrated circuit switching device responsive to atleast one external on/off control signal, the switching devicecomprising: a switch package; a first input/output lead external to andextending into the switch package; a second input/output lead externalto and extending into the switch package; a control lead external to andextending into the switch package; internal to the switch package abi-directional field-effect transistor including a first input/outputterminal, a second input/output terminal and a gate terminal, the firstinput/output terminal being coupled to the first input/output lead andthe second input/output terminal being coupled to the secondinput/output lead wherein the transistor passes bi-directional externaldata signals between the first and second input/output leads when thetransistor is turned on and blocks passage of bi-directional externaldata signals between the first and second input/output leads when thetransistor is turned off; wherein the field-effect transistor has achannel length and a channel width, and a ratio of the channel length tothe channel width is selected such that the transistor has a resistancegreater than zero and no more than about 10 ohms and exhibits a timeconstant greater_than zero and no more than 0.5 nanoseconds; andinternal to the switch package a driver circuit wherein the drivercircuit is coupled to the gate terminal of the field-effect transistor,wherein the driver circuit is coupled to the control lead, wherein thecontrol lead is for receiving the at least one external on/off controlsignal and wherein the driver circuit provides an internal on/offcontrol signal to the gate terminal of the field-effect transistor inresponse to the at least one external on/off control signal appliedexternal to the switch package to the control lead, whereby thetransistor is turned off or on.
 2. The device of claim 1 , wherein saidtransistor is a P-channel transistor.
 3. The device of claim 1 , whereinsaid transistor is an N-channel transistor.
 4. The device of claim 1 ,wherein the ratio of the channel length to the channel width is no morethan 0.0015.
 5. The device of claim 1 wherein the resistance between thefirst and second input/output leads is greater than zero and no morethan about 10 ohms.
 6. The device of claim 1 , wherein the switchpackage, the first input/output lead, the second input/output lead andthe control lead provide a board level switch.
 7. An integrated circuitswitching device responsive to at least one external on/off controlsignal, the switching device comprising: a switch package; a firstinput/output lead external to and extending into the switch package; asecond input/output lead external to and extending into the switchpackage; a control lead external to and extending into the switchpackage; internal to the switch package a bidirectional field-effecttransistor including a first input/output terminal, a secondinput/output terminal and a gate terminal, the first input/outputterminal being coupled to the first input/output lead and the secondinput/output terminal being coupled to the second input/output lead,wherein the transistor passes bidirectional external data signalsbetween the first and second input/output leads when the transistor isturned on and blocks passage of bidirectional external data signalsbetween the first and second input/output leads when the transistor isturned off; wherein the field-effect transistor has a channel length anda channel width, and a ratio of the channel length to the channel widthis selected such that the transistor exhibits a time constant greaterthan zero and no more than 0.5 nanoseconds; and internal to the switchpackage a driver circuit wherein the driver circuit is coupled to thegate terminal of the field-effect transistor, wherein the driver circuitis coupled to the control lead, wherein the control lead is forreceiving the at least one external on/off control signal and whereinthe driver circuit provides an internal on/off control signal to thegate terminal of the field-effect transistor in response to the at leastone external on/off control signal applied external to the switchpackage to the control lead, whereby the transistor is turned off or on.8. The device of claim 7 , wherein said transistor is a P-channeltransistor.
 9. The device of claim 7 , wherein said transistor is anN-channel transistor.
 10. The device of claim 7 , wherein the switchpackage, the first input/output lead, the second input/output lead andthe control lead provide a board level switch.
 11. An integrated circuitswitching device responsive to at least one external on/off controlsignal, the switching device comprising: a switch package; a firstinput/output lead external to and extending into the switch package; asecond input/output lead external to and extending into the switchpackage; a control lead external to and extending into the switchpackage; internal to the switch package a bidirectional field-effecttransistor including a first input/output terminal, a secondinput/output terminal and a gate terminal, the first input/outputterminal being coupled to the first input/output lead and the secondinput/output terminal being coupled to the second input/output leadwherein the transistor passes bidirectional external data signalsbetween the first and second input/output leads when the transistor isturned on and blocks passage of bidirectional external data signalsbetween the first and second input/output leads when the transistor isturned off; wherein the field-effect transistor has a channel length anda channel width, and a ratio of the channel length to the channel widthis greater than zero and no more than 0.0015 and exhibits a timeconstant greater than_zero and no more than 0.5 nanoseconds; andinternal to the switch package a driver circuit wherein the drivercircuit is coupled to the gate terminal of the field-effect transistor,wherein the driver circuit is coupled to the control lead, wherein thecontrol lead is for receiving the at least one external on/off controlsignal and wherein the driver circuit provides an internal on/offcontrol signal to the gate terminal of the field-effect transistor inresponse to the at least one external on/off control signal appliedexternal to the switch package to the control lead, whereby thetransistor is turned off or on.
 12. The device of claim 11 , whereinsaid transistor is a P-channel transistor.
 13. The device of claim 11 ,wherein said transistor is an N-channel transistor.
 14. The device ofclaim 11 , wherein the switch package, the first lead, the second leadand the control lead provide a board level switch.
 15. An integratedcircuit switching device responsive to at least one external on/offcontrol signal, the switching device comprising: a switch package;multiple respective first input/output leads external to and extendinginto the switch package; multiple respective second input/output leadsexternal to and extending into the switch package; at least one controllead external to and extending into the switch package; internal to theswitch package multiple respective bidirectional field-effecttransistors, each including a respective a first input/output terminaland a respective second input/output terminal and a respective gateterminal, each respective first input/output terminal being coupled to arespective first input/output lead and each respective secondinput/output terminal being coupled to a respective second input/outputlead, wherein each respective transistor respectively passesbidirectional individual external data signals between respectiveindividual first and second input/output leads when the respectivetransistor is turned on and respectively blocks passage of bidirectionalindividual external data signals between respective individual first andsecond input/output leads when the respective transistor is turned off;wherein the field-effect transistor has a channel length and a channelwidth, and a ratio of the channel length to the channel width for eachtransistor is selected such that each transistor has a resistancegreater than_zero no more than 10 ohms and exhibits a time constantgreater than zero and no more than 0.5 nanoseconds; and internal to theswitch package at least one driver circuit wherein the driver circuit iscoupled to the multiple respective gate terminals of the multiplerespective field-effect transistor, wherein the driver circuit iscoupled to the at least one control lead, wherein the at least onecontrol lead is for receiving the at least one respective externalon/off control signal and wherein the driver circuit provides respectiveinternal on/off control signals to respective gate terminals of at leasttwo of the respective field-effect transistors in response to the atleast one external on/off control signal applied external to the switchpackage to the at least one control lead.
 16. The device of claim 15 ,wherein the ratio of the channel length to the channel width of eachtransistor is no more than 0.0015.
 17. The device of claim 15 , whereineach respective first input/output terminal is directly connected to arespective individual first input/output lead and each respective secondinput/output terminal is connected directly to a respective individualsecond input/output lead.
 18. The device of claim 15 wherein themultiple respective first input/output terminals are coupled to themultiple respective first input/output leads and the multiple respectivesecond input/output terminals are coupled to the multiple respectivesecond input/output leads such that the resistance between the multiplefirst and second input/output leads is greater than zero and no morethan about 10 ohms.
 19. An integrated circuit switching deviceresponsive to at least one external on/off control signal, the switchingdevice comprising: a switch package; multiple respective firstinput/output leads external to and extending into the switch package;multiple respective second input/output leads external to and extendinginto the switch package; at least one control lead external to andextending into the switch package; internal to the switch packagemultiple respective bidirectional field-effect transistors, eachincluding a respective a first input/output terminal and a respectivesecond input/output terminal and a respective gate terminal, eachrespective first input/output terminal being coupled to a respectivefirst input/output lead and each respective second input/output terminalbeing coupled to a respective second input/output lead, wherein eachrespective transistor respectively passes bidirectional individualexternal data signals between respective individual first and secondinput/output leads when the respective transistor is turned on andrespectively blocks passage of bidirectional individual external datasignals between respective individual first and second input/outputleads when the respective transistor is turned off; wherein thefield-effect transistor has a channel length and a channel width, and aratio of the channel length to the channel width for each transistor isselected such that the transistor exhibits a time constant greater thanzero and no more than 0.5 nanoseconds; and internal to the switchpackage at least one driver circuit wherein the driver circuit iscoupled to the multiple respective gate terminals of the multiplerespective field-effect transistor, wherein the driver circuit iscoupled to the at least one control lead, wherein the at least onecontrol lead is for receiving the at least one respective externalon/off control signal and wherein the driver circuit provides respectiveinternal on/off control signals to respective gate terminals of at leasttwo of the respective field-effect transistors in response to the atleast one external on/off control signal applied external to the switchpackage to the at least one control lead.
 20. A fast transmission,integrated circuit switching device responsive to at least one externalon/off control signal, the switching device comprising: a switchpackage; multiple respective first input/output leads external to andextending into the switch package; multiple respective secondinput/output leads external to and extending into the switch package; atleast one control lead external to and extending into the switchpackage; internal to the switch package multiple respectivebidirectional field-effect transistors, each including a respective afirst input/output terminal and a respective second input/outputterminal and a respective gate terminal, each respective firstinput/output terminal being coupled to a respective first input/outputlead and each respective second input/output terminal being coupled to arespective second input/output lead, wherein each respective transistorrespectively passes bidirectional individual external data signalsbetween respective individual first and second input/output leads whenthe respective transistor is turned on and respectively blocks passageof bidirectional individual external data signals between respectiveindividual first and second input/output leads when the respectivetransistor is turned off; wherein the field-effect transistor has achannel length and a channel width, and a ratio of the channel length tothe channel width of each transistor is greater than zero and no morethan 0.0015 and exhibits a time_constant greater than zero and no morethan 0.5 nanoseconds; and internal to the switch package at least onedriver circuit wherein the driver circuit is coupled to the multiplerespective gate terminals of the multiple respective field-effecttransistor, wherein the driver circuit is coupled to the at least onecontrol lead, wherein the at least one control lead is for receiving theat least one respective external on/off control signal and wherein thedriver circuit provides respective internal on/off control signals torespective gate terminals of at least two of the respective field-effecttransistors in response to the at least one external on/off controlsignal applied external to the switch package to the at least onecontrol lead.
 21. An integrated circuit switching device responsive toat least one external on/off control signal and including a firstinput/output node and a second input/output node, said switching deviceoperative to pass or block the bidirectional transmission of externaldata signals between said first node and said second node, saidswitching device comprising: a bidirectional field-effect transistorincluding a first input/output terminal and a second input/outputterminal and a gate terminal, said first terminal being coupled to saidfirst node and said second terminal being coupled to said second node,whereby said transistor passes bidirectional external data signalsbetween said first and second nodes when said transistor is turned onand blocks the passage of external data signals between said first andsecond nodes when said transistor is turned off; wherein saidfield-effect transistor has a channel length and a channel width, andthe ratio of the channel length to the channel width is selected suchthat the transistor exhibits a time constant greater than zero and nomore than 0.5 nanoseconds; and a driver circuit including an externalterminal for receiving the at least one external on/off control signal;wherein said driver circuit provides an internal on/off control signalto said gate terminal of said field-effect transistor, whereby saidtransistor is turned off or on; the ratio of the channel length tochannel width is greater than zero and no more than 0.0015.
 22. Anintegrated circuit switching device responsive to at least onerespective external on/off control signal and including multiplerespective first input/output nodes and multiple respective secondinput/output nodes, said switching device operative to respectively passor block the bidirectional transmission of respective individualexternal data signals between respective individual first nodes andrespective individual second nodes, said switching device comprising:multiple respective field-effect transistors, each including arespective first input/output terminal and a respective secondinput/output terminal and a respective gate terminal, each respectivefirst terminal being coupled to a respective first node and eachrespective second terminal being coupled to a respective second node,whereby each respective transistor respectively passes bidirectionalindividual external data signals between respective individual first andsecond input/output nodes when said respective transistor is turned onand respectively blocks the passage of individual external data signalsbetween respective individual first and second input/output nodes whensaid respective transistor is turned off; wherein each field-effecttransistor has a channel length and a channel width, and the ratio ofthe channel length to the channel width for each transistor is selectedsuch that each transistor exhibits a time constant greater than zero andno more than 0.5 nanoseconds; and at least one driver circuit includinga respective external terminal for receiving the at least one respectiveexternal on/off signal; wherein the driver circuit provides respectiveinternal on/off control signals to respective control terminals of atleast two of said respective field-effect transistors; the ratio of thechannel length to the channel width of each transistor is greater thanzero and no more than 0.0015.
 23. A system comprising: a driver; areceiver; a printed circuit board having a first trace coupled to thedriver and a second trace coupled to the receiver; a switch packagecontaining an integrated circuit device that includes a first fieldeffect transistor and a driver circuit, the first transistor having aninternal resistance greater than zero and less than about 10 ohms and aninternal capacitance, the first transistor including a firstinput/output terminal, a second input/output terminal and a controlterminal, the driver circuit having an output terminal coupled to thecontrol terminal of the first transistor; a first input/output leadcoupled to the first input/output terminal and extending external to thepackage, the first input/output lead being coupled to the first trace ofthe printed circuit board; a second input/output lead coupled to thesecond input/output terminal and extending external to the package, thesecond input/output lead being coupled to the second trace of theprinted circuit board; and a control lead coupled to an input terminalof the driver circuit, the control lead extending external to thepackage, wherein the first transistor is turned on and off in responseto a control signal applied to the control lead, the first transistorbeing configured to pass signals in a bi-directional manner on the buswhen the first transistor is turned on, and the first transistor beingconfigured to block signals on the bus when the first transistor isturned off; the system exhibiting a capacitance of less than 50 pFbetween the second input/output lead and a reference potential, thesystem further exhibiting a time constant greater than zero and no morethan 0.5 nanoseconds.
 24. The device of claim 23 , wherein theresistance is in the range of 2-3 ohms.
 25. The device of claim 23 ,wherein the internal capacitance is in the range of a few picofarads.